The invention relates to power switches such as power transistors and diodes and in particular to a method for reducing switching loss in a power switch, e.g. a pulse-width-modulated power switch.
The switching losses constitute the major limitation to the use of power switches at high switching frequencies such as those which are required for instance in a power converter in order to reduce the mass of magnetic and capacitive components.
Several snubber circuits have been proposed so far for solving this important problem and among other patents relating to the subject is U.S. Pat. No. 4,669,023. However, all prior art snubber circuits have the disadvantage that they only have a low efficiency so that any power loss saving of the power switch was paid for by the inefficiency of the snubber circuit itself resulting in little total power gain. The reasons for the low efficiency of the state-of-the-art snubber circuits are the following.
Generally the object of the snubber circuit was to relieve the main power switch of the voltage and current stress associated with power switching and many of the snubber circuits use very inefficient techniques resulting in a total decrease in efficiency.
In most prior art snubber circuits, the power switch is used for providing the energy to the circuit, which has a double consequence: 1) an additional stress is put on the power switch, and 2) the power switch is chosen with a low resistance, but this constitutes a handicap for the switching part of its working cycle because a low resistance is normally incompatible with a high switching speed.
In other arrangements, the energy used by the circuit is taken from the power supply and is returned to the input. Hence a low total efficiency is achieved. An example of zero voltage switching converter of this kind is disclosed in U.S. Pat. No. 4,959,764.